1. Field of the Invention
The present invention relates generally to analog circuits, and more specifically, to a circuit for linearizing the output of a differential amplifier core.
2. Background Information
FIG. 1 illustrates a circuit diagram of a prior art differential pair amplifier circuit. The differential amplifier circuit includes transistors Q1 and Q2, emitter degeneration resistors R.sub.E1 and R.sub.E2, load resistors R.sub.C1 and R.sub.C2, and a current source I. Differential inputs V.sub.i+ and V.sub.i- are applied to the bases of transistors Q1 and Q2, and the differential outputs V.sub.o+ and V.sub.o- are provided at the collectors of the transistors Q1 and Q2, respectively. The currents I.sub.E1 and I.sub.E2 through resistors R.sub.E1 and R.sub.E2, respectively, are: EQU I.sub.E1 =((V.sub.i+ -VBE.sub.1)-V.sub.E)/R.sub.E1, and EQU I.sub.E2 =((V.sub.i- -VBE.sub.2)-V.sub.E)/R.sub.E2,
where PA1 where
VBE.sub.1 is the base-emitter voltage of Q1 and VBE.sub.2 is the base-emitter voltage of Q2. PA2 K=Boltzmann's constant PA2 T=absolute temperature PA2 q=electron charge.
In common mode, where V.sub.i+ =V.sub.i-, the circuit is balanced such that half of the current I flows through Q1 (I.sub.E1) and half of the current flows through Q2 (I.sub.E2). In the differential mode, where V.sub.i+ and V.sub.i- differ, the amplifier circuit of FIG. 1 becomes non-linear, since VBE.sub.1 and VBE.sub.2 vary with current in a non-linear manner. The base-emitter voltage difference (VBE.sub.1 -VBE.sub.2) of transistors Q1 and Q2 is related to the ratio of collector currents by the expression: EQU .DELTA.VBE=(KT/q)*ln(I.sub.C1 /I.sub.C2),
With an input V.sub.i+ -V.sub.i-, the voltage V.sub.E1 -V.sub.E2 across degeneration resistors R.sub.E1 and R.sub.E2 is: EQU V.sub.E1 -V.sub.E2 =(V.sub.i+ -VBE.sub.1)-(V.sub.i- -VBE.sub.2), or EQU V.sub.E1 -V.sub.E2 =(V.sub.i+ -V.sub.i-)-.DELTA.VBE.
With R.sub.E1 =R.sub.E2 =R.sub.E, and R.sub.C1 =R.sub.C2 =R.sub.C, the output V.sub.o+ -V.sub.o- is: ##EQU1##
Thus, because the signal across the degeneration resistors R.sub.E1 and R.sub.E2 is not V.sub.i+ -V.sub.i-, but ((V.sub.i+ -V.sub.i-)-.DELTA.VBE), the output is non-linear with respect to (V.sub.i+ -V.sub.i-).
FIG. 2 illustrates a prior art technique for linearizing the characteristics of the differential amplifier circuit of FIG. 1. As shown, diode-connected transistors Q3 and Q4 are placed in the load circuits between the positive power supply terminal VCC and the load resistors R.sub.C1 and R.sub.C2, respectively. Assuming R.sub.E1 =R.sub.C1 =R.sub.E2 =R.sub.C2 (i.e., a gain of 1), the effect of the diode-connected transistors Q2 and Q4 is to offset the non-linearity caused by the differential input transistors Q1 and Q2. Thus, as V.sub.i+ =V.sub.i- changes, the current change in R.sub.C1 and associated VBE change in Q3 is the same as the current change in R.sub.E1 and VBE change in Q1, thereby canceling the non-linearity in the output voltage. This technique is referred to as diode-linearization.
The diode-linearization technique shown in FIG. 2 has drawbacks. If a gain of X (i.e., R.sub.C =X * R.sub.E) is desired, where "X" is a positive whole number greater than 1, then X diode-connected transistors are required in the load. This adds to the number of VBEs in the circuit and reduces the headroom on the output (i.e., reducing the output voltage swing). Accordingly, there is a need in the technology for a method and apparatus to linearize the characteristics of such a differential amplifier.